The invention relates to fractional-N phase locked loops, more particularly to Sigma-Delta controlled fractional-N phase locked loop modulators used for generating continuous phase modulation, and still more particularly to techniques for eliminating nonlinearities in PLL operation.
Phase locked loops (PLLs) are well known, and are useful for generating oscillating signals in many types of circuits, including but not limited to radio circuitry. In digital communication systems, for example in mobile telephone communications operating under the GSM or DCS systems, PLLs may be employed to effect continuous phase modulation (CPM) of a carrier signal.
FIG. 1 is a block diagram of a conventional integer-divide PLL 100. A phase (frequency) detector 101 compares the phase of a signal supplied by a reference oscillator 103 with the phase of a feedback signal supplied by a frequency divider 105. The output of the phase detector, which represents the phase difference between the two input signals, is filtered by a filter 107. The filtered output is then used to control the frequency of an output signal generated by a voltage controlled oscillator (VCO) 109. The output signal from the VCO 109, in addition to being supplied as an output from the PLL, is also supplied as an input to the frequency divider 105, and is thus the source of the feedback source. The PLL 100 is governed by the following equations:                                                                         i                e                            =                              xe2x80x83                            ⁢                                                K                  P                                ⁡                                  (                                                            ϕ                      R                                        -                                                                  ϕ                        o                                            N                                                        )                                                                                                                                          ϕ                  o                                =                                  xe2x80x83                                ⁢                                                      i                    e                                    ⁢                                      Z                    ⁡                                          (                      s                      )                                                        ⁢                                                            K                      V                                        s                                                              ,                                                          (        1        )            
where s, Kp, Z(s), and KV are the complex frequency, phase detector gain, loop-filter trans-impedance, and VCO gain, respectively, and xcfx86R, xcfx86o, and ie, are the reference phase (or frequency as 2xcfx80f=s*xcfx86), the VCO phase, and the phase-detector error current, respectively.
Solving the above equations for xcfx86o yields the well-known result that fo=Nxc2x7fR, that is, the VCO frequency is an integer multiple of the reference frequency.
Since the loop response time to a change in N (e.g., when a new channel is selected) is proportional to 1/fR (i.e., it takes a certain number of reference cycles to settle) and the minimum channel spacing equals fR, there are conflicting considerations involved in the choice of reference frequency. That is, it would be desirable to set a low value for fR to reduce the minimum channel spacing. However, such a setting would result in a larger loop response time, which is undesirable.
To get around the above restriction on channel spacing, fractional-N PLLs have been devised. By employing a variable-modulus divider, rather than an integer divider, it is possible to achieve more flexible divide ratios. For example, performing three successive divisions by 20 followed by one division by 21 results in an average division factor of (3xc2x720+21)/4=20.25 and a channel spacing of fR/4. Due to the repetitive nature of this variable modulus division, however, spurious tones will be generated (here at foxc2x1nxc2x7fR) that will modulate the VCO.
To address these problems, xcexa3xcex94 modulators have been employed to shape the spurious response of the fractional-N divider. If one examines a typical xcexa3xcex94 noise density distribution, it can be seen that the spurious tone is replaced by a spectrum of spurious tones with most of the spurious energy being pushed out in frequency, well beyond the bandwidth of the PLL, essentially being centered around fR/2, where fr is the clocking rate of the xcexa3xcex94 modulator. A thermal noise floor (e.g., thermal noise attributable to the divider circuitry) is also included. As a result of the shaping performed by the xcexa3xcex94 modulator, this spurious energy will have a substantially reduced effect on the output signal from the PLL.
xcexa3xcex94-controlled fractional-N PLLs are often used in radio systems for generating spurious-free local oscillator frequencies and to allow faster frequency jumps. By controlling the divider ratio with a Sigma-Delta modulator, modulation with a constant envelope can be generated. By using these properties of the fractional-N PLL, compact radio architectures for constant envelope systems (e.g., GSM, DCS) can be developed. This also means that the complete radio can be integrated in the same ASIC.
An exemplary embodiment of a xcexa3xcex94 fractional-N PLL 200 is depicted in FIG. 2. The phase detector 201, reference oscillator 203, filter 207 and VCO 209 are analogous to those counterpart elements described with respect to FIG. 1, and therefore need not be described here in detail. The frequency divider 205 in this case is capable of dividing by any integer modulus in the range Nxc2x1M, and has two inputs: one for receiving a value for N, and another for receiving a value of M. By appropriately varying the value of M as described above, an effective division modulus of N+xcex4N can be achieved. A xcexa3xcex94 modulator 211 is provided that receives a desired channel value, and generates therefrom appropriate values for N and M. A first-order xcexa3xcex94 modulator may be used, but this is not essential; higher-order xcexa3xcex94 modulators may be used in alternative embodiments.
The xcexa3xcex94 noise will be suppressed by the loop response (i.e., if the loop bandwidth is not too wide), but to avoid spurious tones due to xcexa3xcex94-modulator limit cycles (i.e., a repetitive behavior associated with having a period time that is too short), extra noise (xe2x80x9cditherxe2x80x9d) is typically added to the xcexa3xcex94 noise in order to further randomize the xcexa3xcex94 noise. The resultant value is then quantized, which adds its own quantization noise, eq(k). The resultant value M, which is generated at the output of the xcexa3xcex94 modulator 211, is supplied to one of the modulus inputs of the frequency divider 205.
To make the noise shaping possible, the divider modulus should not be chosen to be only the two closest integer factors, but should instead be varied between, for example, Nxe2x88x92M, . . . , N+M. This extra modulus range is required if noise is to be pushed out in frequency, away from the VCO carrier; otherwise, the loop filter will not be able to suppress the xcexa3xcex94 noise. As a consequence of this extended divider modulus range, the instantaneous phase error will be increased. The xcexa3xcex94-loop equations then become:                                                                         i                e                            =                              xe2x80x83                            ⁢                                                K                  P                                ⁡                                  (                                                            ϕ                      R                                        -                                                                  ϕ                        o                                                                    N                        +                                                  δ                          ⁢                                                      xe2x80x83                                                    ⁢                          N                                                                                      +                                          N                                              Δ                        ⁢                                                  xe2x80x83                                                ⁢                        Σ                                                                              )                                                                                                                                          ϕ                  o                                =                                  xe2x80x83                                ⁢                                                      i                    e                                    ⁢                                      Z                    ⁡                                          (                      s                      )                                                        ⁢                                                            K                      V                                        s                                                              ,                                                          (        2        )            
where N+xcex4N and Nxcexa3xcex94 represent the fractional division ratio and the xcexa3xcex94-modulator noise, respectively.
FIG. 3 is a block diagram of a typical embodiment of the conventional phase detector 201. The use of first and second digital latches 301, 303 enables multiple states (not shown in FIG. 3) and, hence, an extended range of the phase detector 201. In operation, the first latch 301 controls whether a first charge pump 305 is on or off. Similarly, the second latch 303 controls whether the second charge pump 307 is on or off. The first and second charge pumps 305, 307 are connected in series, with the phase detector output current, Iout, being supplied at the connection point between the two charge pumps. The amount of phase detector output current, Iout, is related to whether none, one, or both of the first and second charge pumps 305, 307 are turned on. The amount of time that Iout is non-zero is a function of the phase difference between the first and second input signals, fref and prescaler (Presc.). (The prescaler signal may also be referred to as a xe2x80x9cfeedback signalxe2x80x9d, when the phase detector 201 is used in a PLL.) Each of these signals is supplied to a clock input of a respective one of the first and second latches 301, 303. The first of these signals to present a clocking edge causes the output of the corresponding latch to be asserted, which in turn, causes a corresponding one of the first and second charge pumps 305, 307 to turn on. When the clocking edge of the remaining input signal is subsequently asserted, it too causes the output of its corresponding latch to be asserted. The outputs of both the first and second latches 301, 303 are further supplied to respective inputs of a logical AND gate 309, whose output is supplied to the RESET inputs of both the first and second latches 301, 303. Consequently, when the outputs of both latches 301, 303 are asserted, the output of the AND gate 309 will be asserted as well, thereby resetting both latches 301, 303. They are now initialized to repeat the process again for a next cycle. As a result, the output current Iout is either a positive value (being supplied by the first charge pump 305) if the first input signal fref leads the second input signal Presc., or else it is a negative value (being drawn by the second charge pump 307) if the second input signal Presc. leads the first input signal fref.
The phase detector output is often designed with charge pumps having a high-impedance off state. This high-impedance off state effectively turns the loop filter into an integrator (i.e., if the trans-impedance Z(s) is capacitive). A simplified rendition of the charge pump 305 can include a current mirror that supplies current when the xe2x80x9csourcexe2x80x9d signal is asserted. A simplified rendition of the charge pump 307 can include a transistor that is turned on by the xe2x80x9csinkxe2x80x9d signal, so that it draws current when the xe2x80x9csinkxe2x80x9d signal is asserted.
Referring back to FIGS. 2 and 3, when the PLL 201 is properly tracking its reference, fref, both of the phase-detector latches 301, 303 trigger almost simultaneously, due to the fact that the phase difference between the two input signals becomes very small. The reset signal immediately resets the first and second latches 301, 303 and, as a consequence, only short spikes appear at the latch outputs, too fast to turn on the respective first and second charge pumps 305, 307.
In fact, even when there is a small phase error (i.e., a tracking error), the first and second latches 301, 303 will reset too fast for the charge pumps 305, 307 to react. Consequently, the phase-detector transfer function will be characterized by a small dead-band (low-gain region) around the origin. A common technique to combat this dead-band is to utilize a delay circuit 401, which adds a delay xcex94T to the reset signal, as illustrated in FIG. 4. With this extra delay, the up and down pulses will each be long enough to activate the charge pumps, thereby eliminating the dead-band.
Despite the use of the delay circuit 401 as described above, however, the xcexa3xcex94-based fractional-N PLLs reported in the literature often have inferior noise performance compared to their integer-divide counterparts. This has prevented their use in demanding applications, like cellular phones. The origin of this excess noise has conventionally been attributed to the xcexa3xcex94-modulator noise, even though the noise can be made to fall outside the loop bandwidth.
An additional problem when using a xcexa3xcex94-based fractional-N PLL is that any nonlinearity in the analog implementation of the digital PLL will cause xcexa3xcex94 noise to be rectified and folded into the PLL bandwidth. The nonlinearity could be caused by charge pump nonlinearity, reference voltage ringing or substrate coupling.
FIG. 5 is a timing diagram that illustrates typical signals that are generated in a xcexa3xcex94 fractional-N PLL that employs a phase detector such as the one depicted in FIG. 4. The fref and prescaler inputs control the source and sink currents, respectively. After a delay, xcex94T, the reset signal is generated which turns off the current sources. In this example, the prescaler division ratio has increased from a nominal one. It can be seen that the rising edges of the source and sink currents are relatively close to one another, and that the source pulse is longer than the sink pulse.
FIG. 6 is a timing diagram that illustrates the phase-detector signals when the prescaler division ratio has decreased from the nominal one. The rising edges of the source and sink pulses are still relatively close to one another. However, note that in this case, the sink pulse is longer than the source pulse. As a consequence, a mismatch between the sink and source signals generates a nonlinear PLL transfer function. As used herein, the term xe2x80x9cmismatchxe2x80x9d is used to refer to the situation in which the respective amplitudes of the sink and source charge pump current sources are not the same. When this occurs, the charge inserted into the loop filter for a given positive phase difference between the signals at the input of the phase-detector is not the same as the charge inserted into the loop filter for an equal but negative phase difference between these signals. Hence, the nonlinear performance of the PLL.
There is therefore a need to provide methods and apparatuses for ensuring linear operation of PLLs.
It should be emphasized that the terms xe2x80x9ccomprisesxe2x80x9d and xe2x80x9ccomprisingxe2x80x9d, when used in this specification, are taken to specify the presence of stated features, integers, steps or components; but the use of these terms does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.
In accordance with one aspect of the present invention, the foregoing and other objects are achieved in methods and apparatuses such as a phase detector that includes a first input that receives a first signal, a second input that receives a second signal, and a comparison circuit that generates an output current in proportion to a phase difference between the first signal and the second signal. An operating point circuit selectively maintains a first operating point of the phase detector when a phase of the first signal leads a phase of the second signal, and maintains a second operating point of the phase detector when the phase of the first signal lags the phase of the second signal. The first and second operating points are different from one another. Each of the first and second operating points causes the output current to vary substantially linearly for a predetermined range of both positive and negative phase differences between the first signal and the second signal.
Selective maintenance of the operating point may be done in any of a number of ways. For example, in some embodiments, either a constant sink current or a constant source current is alternatively added to the phase detector output current as a function of a direction of change in a frequency difference between the first signal and the second signal.
In other embodiments, selective maintenance of the operating point may be achieved within the phase detector by generating a source signal in response to an activating edge of the first signal, and generating a sink signal in response to an activating edge of the second signal. If the first signal leads the second signal, then a delayed source signal is generated, and both the source and sink signals are reset in response to assertion of both the delayed source signal and the sink signal. If the first signal lags the second signal, then a delayed sink signal is generated, and both the source and sink signals are reset in response to assertion of both the source signal and the delayed sink signal.